MC10175 Datasheet, PDF (1/5 Pages) ON Semiconductor – Quint Latch

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five D type
latches with common reset and a common two–input clock. Data is transferred
on the negative edge of the clock and latched on the positive edge. The two
clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while the clock
is low. The outputs are latched on the positive transition of the clock. While the
clock is in the high state, a change in the information present at the data inputs
will not affect the output information. The reset input is enabled only when the
clock is in the high state.
PD = 400 mW typ/pkg (No Load)
tpd = 2.5 ns typ (Data to Output)
tr, tf = 2.0 ns typ (20%–80%)
D0 10
LOGIC DIAGRAM
DQ
CR
14 Q0
D1 12
D2 13
D3 9
D4 5
C0 6
C1 7
RESET 11
DQ
CR
15 Q1
DQ
CR
2 Q2
DQ
CR
3 Q3
DQ
CR
4 Q4
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
MC10175
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
VCC1
1
Q2
2
Q3
3
Q4
4
D4
5
C0
6
C1
7
VEE
8
16
VCC2
15
Q1
14
Q0
13
D2
12
D1
11
RESET
10
D0
9
D3
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
TRUTH TABLE
D C0
C1
Reset Qn+1
LL
L
HL
L
XH
X
XX
H
XH
X
XX
H
X
L
X
H
L
Qn
L
Qn
H
L
H
L
3/93
© Motorola, Inc. 1996
3–126
REV 5