MC10162 Datasheet, PDF (1/4 Pages) ON Semiconductor – Binary to 1-8 Decoder (High)

MC10162
Binary to 1-8 Decoder
(High)
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other
outputs are low. The enable inputs, when either or both are high, force
all outputs low.
The MC10162 is a true parallel decoder. No series gating is used
internally, eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of
the two enable inputs is used as the data input, while the other is used
as a data enable input.
A complete mux/demux operation on 16 bits for data distribution is
illustrated in Figure 1 of the MC10161 data sheet.
• P_D = 315 ns typ/pkg (No Load)
• t_pd = 4.0 ns typ
• t_r, t_f = 2.0 ns typ (20%–80%)
E0Ą2
E1Ą15
AĄ7
BĄ9
CĄ14
LOGIC DIAGRAM
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
6ĄQ0
5ĄQ1
4ĄQ2
3ĄQ3
13ĄQ4
12ĄQ5
11ĄQ6
10ĄQ7
INPUTS
TRUTH TABLE
OUTPUTS
E0 E1 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L
L LLL H
L
L
L
L
L
L
L
L
L LLH L
HL
L
L
L
L
L
L
L LHL L
L
H
L
L
L
L
L
L
L LHH L
L
LHL
L
L
L
L
L HL L L
L
L
L
H
L
L
L
L
L HLH L
L
L
L
L
HL
L
L
L HH L L
L
L
L
L
LH
L
L
L HHH L
L
L
L
L
L
L
H
H
X XXX L
L
L
L
L
L
L
L
X
H XXX L
L
L
L
L
L
L
L
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC10162L
AWLYYWW
1
16
MC10162P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10162
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
DIP PIN ASSIGNMENT
V_CC1
1
E0
2
Q3
3
Q2
4
Q1
5
Q0
6
A
7
V_EE
8
16
V_CC2
15
E1
14
C
13
Q4
12
Q5
11
Q6
10
Q7
9
B
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
Device
Package
Shipping
MC10162L
CDIP–16
25 Units / Rail
MC10162P
PDIP–16
25 Units / Rail
MC10162FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10162/D