MC10138 Datasheet, PDF (1/5 Pages) ON Semiconductor – Bi-Quinary Counter

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Bi-Quinary Counter
The MC10138 is a four bit counter capable of divide by two, five, or ten
functions. It is composed of four set–reset master–slave flip–flops. Clock
inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous “set” or
“clear.” Individual set and common reset inputs are provided, as well as
complementary outputs for the first and fourth bits.
PD = 370 mW typ/pkg (No Load)
ftog = 150 MHz typ
tr, tf = 2.5 ns typ (20%–80%)
S0 Q0
11
15
LOGIC DIAGRAM
S1 Q1
10
13
S2 Q2
6
4
S3
Q3
5
2
12
Clock
S
D1 Q
Q’
C1 Q
R
S
D1 Q
D2 Q’
C2 Q
R
S
D1 Q
C1 Q’
C2 Q
R
S
D1 Q’
D2 Q
C2 Q
R
9
Reset
14
7
3
Q0 C2
Q3
VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8
COUNTER TRUTH TABLES
BI–QUINARY
BCD
(Clock connected to C2
(Clock connected to C1
and Q3 connected to C1)
and Q0 connected to C2)
COUNT Q1 Q2 Q3 Q0
COUNT Q0 Q1 Q2 Q3
0
LLLL
1
HL L L
2
LHL L
3
HHL L
0
LLLL
1
HL L L
2
LHL L
3
HHL L
4
L LHL
5
L L LH
6
HL LH
7
LHLH
4
L LHL
5
HLHL
6
L HH L
7
HHH L
8
HH L H
9
L LHH
8
L L LH
9
HL LH
COUNTER STATE DIAGRAM — POSITIVE LOGIC
CLOCK CONNECTED TO C2
0
Q0 CONNECTED TO C2
0
1
2
3
MC10138
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
VCC1
1
Q3
2
Q3
3
Q2
4
S3
5
S2
6
C2
7
VEE
8
16
VCC2
15
Q0
14
Q0
13
Q1
12
C1
11
S0
10
S1
9
RESET
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
4
4
7
1
5
6
3
2
14
10
11
15
12
13
9
8
7
6
5
3/93
© Motorola, Inc. 1996
3–41
REV 5