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MC10135_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual J-K Master-Slave Flip-Flop | |||
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MC10135
Dual J-K Master-Slave
Flip-Flop
The MC10135 is a dual masterâslave dc coupled JâK flipâflop.
Asynchroâ nous set (S) and reset (R) are provided. The set and reset
inputs override the clock.
A common clock is provided with separate JâK inputs. When the
clock is static, the JâK inputs do not effect the output.
The output states of the flipâflop change on the positive transition of
the clock.
⢠PD = 280 mW typ/pkg (No Load)
⢠fTog = 140 MHz typ
⢠tpd = 3.0 ns typ
⢠tr, tf = 2.5 ns typ (20%â80%)
DIP PIN ASSIGNMENT
LOGIC DIAGRAM
S1 5
VCC1
1
Q1
2
Q1
3
R1
4
S1
5
K1
6
J1
7
VEE
8
16
VCC2
15
Q2
14
Q2
13
R2
12
S2
11
K2
10
J2
9
C
J1 7
K1 6
R1 4
C9
S2 12
J2 10
K2
11
R2 13
Pin assignment is for DualâinâLine Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 18 of the ON Semiconductor MECL
Data Book (DL122/D).
Q1
2
Q1
3
Q2
15
Q2
14
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
RâS TRUTH TABLE
R
S
Qn+1
L
L
Qn
L
H
H
H
L
L
H
H
N.D.
N.D. = Not Defined
CLOCK JâK TRUTH TABLE*
J
K
Qn+1
L
L
Qn
H
L
L
L
H
H
H
H
Qn
* Output states change on positive
transition of clock for JâK input
condition present.
http://onsemi.com
CDIPâ16
L SUFFIX
CASE 620
PDIPâ16
P SUFFIX
CASE 648
PLCCâ20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10135L
AWLYYWW
1
16
MC10135P
AWLYYWW
1
1
10135
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10135L
CDIPâ16
25 Units / Rail
MC10135P
PDIPâ16
25 Units / Rail
MC10135FN
PLCCâ20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 â Rev. 7
Publication Order Number:
MC10135/D
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