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MC10131_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual Type D Master-Slave Flip-Flop | |||
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MC10131
Dual Type D Master-Slave
Flip-Flop
The MC10131 is a dual masterâslave type D flipâflop.
Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flipâflop may be clocked separately by
holding the common clock in the low state and using the enable inputs
for the clocking function. If the common clock is to be used to clock
the flipâflop, the Clock Enable inputs must be in the low state. In this
case, the enable inputs perform the function of controlling the
common clock.
The output states of the flipâflop change on the positive transition of
the clock. A change in the information present at the data (D) input
will not affect the output information at any other time due to master
slave construction.
⢠PD = 235 mW typ/pkg (No Load)
⢠FTog = 160 MHz typ
⢠tpd = 3.0 ns typ
⢠tr, tf = 2.5 ns typ (20%â80%)
DIP PIN ASSIGNMENT
VCC1
1
Q1
2
Q1
3
R1
4
S1
5
CE1
6
D1
7
VEE
8
16
VCC2
15
Q2
14
Q2
13
R2
12
S2
11
CE2
10
D2
9
CC
Pin assignment is for DualâinâLine Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
LOGIC DIAGRAM
S1 5
D1 7
CE1 6
Q1
2
Q1
3
R1 4
CC 9
R2 13
CE2 11
D2 10
Q2
14
Q2
15
S2 12
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 â Rev. 7
http://onsemi.com
CDIPâ16
L SUFFIX
CASE 620
PDIPâ16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC10131L
AWLYYWW
1
16
MC10131P
AWLYYWW
1
1
PLCCâ20
FN SUFFIX
CASE 775
10131
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CLOCKED TRUTH TABLE
C
D
Qn+1
L
X
Qn
H
L
L
H
H
H
C = CE + CC.A clock H is a clock transition from a low to a
high state.
RâS TRUTH TABLE
R
S
Qn+1
L
L
Qn
L
H
H
H
L
L
H
H
N.D.
N.D. = Not Defined
ORDERING INFORMATION
Device
Package
Shipping
MC10131L
CDIPâ16
25 Units / Rail
MC10131P
PDIPâ16
25 Units / Rail
MC10131FN
PLCCâ20
46 Units / Rail
Publication Order Number:
MC10131/D
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