MC10125 Datasheet, PDF (1/8 Pages) Motorola, Inc – Quad MECL to TTL Transistor

MC10125
Quad MECL to TTL
Translator
The MC10125 is a quad translator for interfacing data and control
signals between the MECL section and saturated logic sections of
digital systems. The MC10125 incorporates differential inputs and
Schottky TTL “totem pole” outputs. Differential inputs allow for use
as an inverting/ non–inverting translator or as a differential line
receiver. The V_BB reference voltage is available on pin 1 for use in
single–ended input biasing. The outputs of the MC10125 go to a low
logic level whenever the inputs are left floating.
Power supply requirements are ground, +5.0 Volts and –5.2 Volts.
Propagation delay of the MC10125 is typically 4.5 ns. The MC10125
has fanout of 10 TTL loads. The dc levels are MECL 10,000 in and
Schottky TTL, or TTL out. This device has an input common mode
noise rejection of ± 1.0 Volt.
An advantage of this device is that MECL level information can be
received, via balanced twisted pair lines, in the TTL equipment. This
isolates the MECL logic from the noisy TTL environment. This device
is useful in computers, instrumentation, peripheral controllers, test
equipment and digital communications systems.
• P_D = 380 mW typ/pkg (No Load)
• t_pd = 4.5 ns typ (50% to + 1.5 Vdc out)
• t_r, t_f = 2.5 ns typ (1.0 V to 2.0 V)
LOGIC DIAGRAM
2
3
4
6
7
5
Gnd
= PIN 16
10
11
12 ^{VCC (+5.0Vdc) = PIN 9}
V_EE (-5.2Vdc) = PIN 8
14
15
13
1
V_BB*
* V_BB to be used to supply bias to the MC10125 only and bypassed (when used)
with 0.01 µF to 0.1 µF capacitor to ground (0 V). V_BB can source < 1.0 mA.
When the input pin with the bubble goes positive, the output goes negative.
DIP PIN ASSIGNMENT
V_BB
1
A_IN
2
A_IN
3
A_OUT
4
B_OUT
5
B_IN
6
B_IN
7
V_EE
8
16
GND
15
D_IN
14
D_IN
13
D_OUT
12
C_OUT
11
C_IN
10
C_IN
9
V_CC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10125L
AWLYYWW
1
16
MC10125P
AWLYYWW
1
1
10125
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10125L
CDIP–16
25 Units / Rail
MC10125P
PDIP–16
25 Units / Rail
MC10125FN
PLCC–20
46 Units / Rail
Publication Order Number:
MC10125/D