MC10124 Datasheet, PDF (1/7 Pages) ON Semiconductor – Quad TTL to MECL Translator

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad TTL to MECL Translator
The MC10124 is a quad translator for interfacing data and control signals
between a saturated logic section and the MECL section of digital systems. The
MC10124 has TTL compatible inputs, and MECL complementary open–emitter
outputs that allow use as an inverting/ non–inverting translator or as a
differential line driver. When the common strobe input is at the low logic level, it
forces all true outputs to a MECL low logic state and all inverting outputs to a
MECL high logic state.
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels are
standard or Schottky TTL in, MECL 10,000 out.
An advantage of this device is that TTL level information can be transmitted
differentially, via balanced twisted pair lines, to the MECL equipment, where the
signal can be received by the MC10115 or MC10116 differential line receivers.
The MC10124 is useful in computers, instrumentation, peripheral controllers,
test equipment, and digital communications systems.
PD = 380 mW typ/pkg (No Load)
tpd = 3.5 ns typ (+ 1.5 Vdc in to 50% out)
tr, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
5
4
6
2
7
3
1
10
12
15
11
13
14
Gnd
=
VCC (+5.0Vdc) =
VEE (–5.2Vdc) =
PIN 16
PIN 9
PIN 8
MC10124
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
BOUT
1
AOUT
2
BOUT
3
AOUT
4
AIN
5
COMMON
6
STROBE
BIN
7
VEE
8
16
GND
15
COUT
14
DOUT
13
DOUT
12
COUT
11
DIN
10
CIN
9
VCC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–82
REV 5