MC10123_02 Datasheet, PDF (1/4 Pages) ON Semiconductor – Triple 4-3-3-Input Bus Driver

MC10123
Triple 4-3-3-Input Bus
Driver
The MC10123 consists of three NOR gates designed for bus driving
applications on card or between cards. Output low logic levels are
specified with V_OL = –2.1 Vdc so that the bus may be terminated to
–2.0 Vdc. The gate output, when low, appears as a high impedance to
the bus, because the output emitter– followers of the MC10123 are
“turned–off.” This eliminates discontinuities in the characteristic
impedance of the bus.
The V_OH level is specified when driving a 25–ohm load terminated
to –2.0 Vdc, the equivalent of a 50–ohm bus terminated at both ends.
Although 25 ohms is the lowest characteristic impedance that can be
driven by the MC10123, higher impedance values may be used with
this part. A typical 50–ohm bus is shown in Figure 1.
• P_D = 310 mW typ/pkg (No Load)
• t_pd = 3.0 ns typ
• t_r, t_f = 2.5 ns typ (20%–80%)
DIP
PIN ASSIGNMENT
V_CC1
1
B_OUT
2
A_OUT
3
A_IN
4
A_IN
5
A_IN
6
A_IN
7
V_EE
8
16
V_CC2
15
C_OUT
14
C_IN
13
C_IN
12
C_IN
11
B_IN
10
B_IN
9
B_IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC10123L
AWLYYWW
1
16
MC10123P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10123
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10123L
CDIP–16
25 Units / Rail
MC10123P
PDIP–16
25 Units / Rail
MC10123FN
PLCC–20
46 Units / Rail
LOGIC DIAGRAM
4
5
3
6
7
9
10
2
11
12
13
14
V_CC1 = PIN 1
15
V_CC2 = PIN 16
V_EE = PIN 8
FIGURE 1 — 50–OHM BUS DRIVER (TYPICAL APPLICATION)
1/3 MC10123
1/3 MC10123
1/3 MC10123
Z_O = 50 Ω
50 Ω
–2.0
VDC
RECEIVERS (MECL GATES)
50 Ω
–2.0
VDC
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10123/D