MC10123 Datasheet, PDF (1/4 Pages) ON Semiconductor – Triple 4-3-3-Input Bus Driver

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple 4-3-3-Input Bus Driver
The MC10123 consists of three NOR gates designed for bus driving
applications on card or between cards. Output low logic levels are specified with
VOL = –2.1 Vdc so that the bus may be terminated to –2.0 Vdc. The gate output,
when low, appears as a high impedance to the bus, because the output emitter–
followers of the MC10123 are “turned–off.” This eliminates discontinuities in the
characteristic impedance of the bus.
The VOH level is specified when driving a 25–ohm load terminated to –2.0
Vdc, the equivalent of a 50–ohm bus terminated at both ends. Although 25
ohms is the lowest characteristic impedance that can be driven by the
MC10123, higher impedance values may be used with this part. A typical
50–ohm bus is shown in Figure 1.
PD = 310 mW typ/pkg (No Load)
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)
MC10123
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
4
5
3
6
7
9
10
2
11
12
13
15
14
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
FIGURE 1 — 50–OHM BUS DRIVER (TYPICAL APPLICATION)
1/3 MC10123
1/3 MC10123
1/3 MC10123
ZO = 50 Ω
50 Ω
–2.0
VDC
RECEIVERS (MECL GATES)
50 Ω
–2.0
VDC
DIP
PIN ASSIGNMENT
VCC1
1
BOUT
2
AOUT
3
AIN
4
AIN
5
AIN
6
AIN
7
VEE
8
16
VCC2
15
COUT
14
CIN
13
CIN
12
CIN
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–78
REV 5