MC10121_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – 4-Wide OR-AND/OR-AND Gate

MC10121
4-Wide OR-AND/OR-AND
Gate
The MC10121 is a basic logic building block providing the
simultaneous OR–AND/OR–AND–Invert function, useful in data
control and digital multiplexing applications.
• P_D = 100 mW typ/pkg (No Load)
• t_pd = 2.3 ns typ
• t_r, t_f = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
4
5
6
7
9
10
2
3
11
12
V_CC1 = PIN 1
13
V_CC2 = PIN 16
14
V_EE = PIN 8
15
DIP
PIN ASSIGNMENT
V_CC1
1
A_OUT
2
A_OUT
3
A1_IN
4
A1_IN
5
A1_IN
6
A2_IN
7
V_EE
8
16
V_CC2
15
A4_IN
14
A4_IN
13
A4_IN
12
A3_IN
11
A3_IN
10
A2_IN, A3_IN
9
A2_IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10121L
AWLYYWW
1
16
MC10121P
AWLYYWW
1
1
10121
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10121L
CDIP–16
25 Units / Rail
MC10121P
PDIP–16
25 Units / Rail
MC10121FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10121/D