MC10117_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate

MC10117
Dual 2-Wide 2-3-Input
OR-AND/OR-AND Gate
The MC10117 is a dual 2–wide 2–3–input
OR–AND/OR–AND–Invert gate. This general purpose logic element
is designed for use in data control, such as digital multiplexing or data
distribution. Pin 9 is common to both gates.
• P_D = 100 mW typ/pkg (No Load)
• t_pd = 2.3 ns typ
• t_r, t_f = 2.2 ns typ (20%–80%)
LOGIC DIAGRAM
4
5
3
6
2
7
9
10
11
14
15
12
13
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
DIP
PIN ASSIGNMENT
V_CC1
1
A_OUT
2
A_OUT
3
A1_IN
4
A1_IN
5
A2_IN
6
A2_IN
7
V_EE
8
16
V_CC2
15
B_OUT
14
B_OUT
13
B1_IN
12
B1_IN
11
B2_IN
10
B2_IN
9
A2_IN, B2_IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10117L
AWLYYWW
1
16
MC10117P
AWLYYWW
1
1
10117
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10117L
CDIP–16
25 Units / Rail
MC10117P
PDIP–16
25 Units / Rail
MC10117FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10117/D