MC10113 Datasheet, PDF (1/8 Pages) Motorola, Inc – Quad Exclusive OR Gate

MC10113
Quad Exclusive OR Gate
The MC10113 is a quad Exclusive OR gate, with an enable common
to all four gates. The outputs may be wire–ORed together to perform a
4–bit comparison function (A = B). The enable is active low.
• P_D = 175 mW typ/pkg (No Load)
• t_pd = 2.5 ns typ
• t_r, t_f = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
E9
V_CC1 = PIN 1
V_CC2 = PIN 16
4
5
2
V_EE = PIN 8
6
3
7
10
11
14
DIP
12
15
PIN ASSIGNMENT
13
V_CC1
1
16
V_CC2
A_OUT
2
15
D_OUT
B_OUT
3
14
C_OUT
A_IN
4
13
D_IN
A_IN
5
12
D_IN
B_IN
6
11
C_IN
B_IN
7
10
C_IN
V_EE
8
9
ENABLE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
TRUTH TABLE
IN E OUTPUT
LLL
L
LHL
H
HL L
H
HH L
L
XXH
L
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10113L
AWLYYWW
1
16
MC10113P
AWLYYWW
1
1
10113
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10113L
CDIP–16
25 Units / Rail
MC10113P
PDIP–16
25 Units / Rail
MC10113FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10113/D