MC10111 Datasheet, PDF (1/5 Pages) ON Semiconductor – Dual 3−Input/3−Ouput NOR Gate

MC10111
Dual 3−Input/3−Ouput NOR
Gate
The MC10111 is designed to drive up to three transmission lines
simul− taneously. The multiple outputs of this device also allow the
wire “OR”−ing of several levels of gating for minimization of gate and
package count.
The ability to control three parallel lines from a single point makes
the MC10111 particularly useful in clock distribution applications
where minimum clock skew is desired. Three V_CC pins are provided
and each one should be used.
• P_D = 80 mW typ/gate (No Load)
• t_pd = 2.4 ns typ (All Outputs Loaded)
• t_r, t_f = 2.2 ns typ (20%−80%)
LOGIC DIAGRAM
2
5
3
6
4
7
12
9
13
10
14
11
V_CC1 = PIN 1,15
V_CC2 = PIN 16
V_EE = PIN 8
DIP
PIN ASSIGNMENT
V_CC1
1
A_OUT
2
A_OUT
3
A_OUT
4
A_IN
5
A_IN
6
A_IN
7
V_EE
8
16
V_CC2
15
V_CC1
14
B_OUT
13
B_OUT
12
B_OUT
11
B_IN
10
B_IN
9
B_IN
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP−16
L SUFFIX
CASE 620
PDIP−16
P SUFFIX
CASE 648
PLCC−20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10111L
AWLYYWW
1
16
MC10111P
AWLYYWW
1
1
10111
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10111L
CDIP−16
25 Units / Rail
MC10111P
PDIP−16
25 Units / Rail
MC10111FN
PLCC−20 46 Units / Rail
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 8
Publication Order Number:
MC10111/D