MC10110 Datasheet, PDF (1/8 Pages) Motorola, Inc – Dual 3-Input/3-Output OR Gate

MC10110
Dual 3-Input/3-Ouput OR
Gate
The ability to control three parallel lines from a single point makes
the MC10110 particularly useful in clock distribution applications
where minimum clock skew is desired. Three VCC pins are provided
and each one should be used.
• PD = 80 mW typ/pkg (No Load)
• tpd = 2.4 ns typ (All Outputs Loaded)
• tr, tf = 2.2 ns typ (20%–80%)
LOGIC DIAGRAM
5
6
2
7
3
4
9
10
12
11
13
14
VCC1 = PIN 1, 15
VCC2 = PIN 16
VEE = PIN 8
DIP
PIN ASSIGNMENT
VCC1
1
AOUT
2
AOUT
3
AOUT
4
AIN
5
AIN
6
AIN
7
VEE
8
16
VCC2
15
VCC1
14
BOUT
13
BOUT
12
BOUT
11
BIN
10
BIN
9
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10110L
AWLYYWW
1
16
MC10110P
AWLYYWW
1
1
10101
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10110L
CDIP–16
25 Units / Rail
MC10110P
PDIP–16
25 Units / Rail
MC10110FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 7
Publication Order Number:
MC10110/D