MC10107_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Triple 2-Input Exclusive OR/ Exclusive NOR Gate

MC10107
Triple 2-Input Exclusive OR/
Exclusive NOR Gate
The MC10107 is a triple–2 input exclusive OR/NOR gate.
• P_D = 40 mW typ/gate (No Load)
• t_pd = 2.8 ns typ
• t_r, t_f = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
4
2
5
3
9
11
7
10
14
12
15
13
3 = (4 • 5) + (4 • 5)
2 = (4 • 5) + (4 • 5)
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
DIP
PIN ASSIGNMENT
V_CC1
1
A_OUT
2
A_OUT
3
A_IN
4
A_IN
5
*NC
6
B_IN
7
V_EE
8
16
V_CC2
15
C_IN
14
C_IN
13
C_OUT
12
C_OUT
11
B_OUT
10
B_OUT
9
B_IN
*NC = No Connection
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10107L
AWLYYWW
1
16
MC10107P
AWLYYWW
1
1
10107
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10107L
CDIP–16
25 Units / Rail
MC10107P
PDIP–16
25 Units / Rail
MC10107FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10107/D