MC10105_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Triple 2-3-2-Input OR/NOR Gate

MC10105
Triple 2-3-2-Input OR/NOR
Gate
The MC10105 is a triple 2–3–2 input OR/NOR gate.
• P_D = 30 mW typ/gate (No Load)
• t_pd = 2.0 ns typ
• t_r, t_f = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4
3
5
2
9
6
10
11
7
13
14
12
15
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
DIP
PIN ASSIGNMENT
V_CC1
1
A_OUT
2
A_OUT
3
A_IN
4
A_IN
5
B_OUT
6
B_OUT
7
V_EE
8
16
V_CC2
15
C_OUT
14
C_OUT
13
C_IN
12
C_IN
11
B_IN
10
B_IN
9
B_IN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10105L
AWLYYWW
1
16
MC10105P
AWLYYWW
1
1
10105
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10105L
CDIP–16
25 Units / Rail
MC10105P
PDIP–16
25 Units / Rail
MC10105FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10105/D