MC10101_02 Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad OR/NOR Gate

MC10101
Quad OR/NOR Gate
The MC10101 is a quad 2–input OR/NOR gate with one input from
each gate common to pin 12.
• P_D = 25 mW typ/gate (No Load)
• t_pd = 2.0 ns typ
• t_r, t_f = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4
2
5
7
3
6
10
14
11
13
15
12
9
V_CC1 = PIN 1
V_CC2 = PIN 16
V_EE = PIN 8
DIP
PIN ASSIGNMENT
V_CC1
1
A_OUT
2
B_OUT
3
A_IN
4
A_OUT
5
B_OUT
6
B_IN
7
V_EE
8
16
V_CC2
15
D_OUT
14
C_OUT
13
D_IN
12
COMMON
INPUT
11
C_OUT
10
C_IN
9
D_OUT
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10101L
AWLYYWW
1
16
MC10101P
AWLYYWW
1
1
10101
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10101L
CDIP–16
25 Units / Rail
MC10101P
PDIP–16
25 Units / Rail
MC10101FN
PLCC–20
46 Units / Rail
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10101/D