MC100LVEP210 Datasheet, PDF (1/8 Pages) ON Semiconductor – Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver

MC100LVEP210
Low-Voltage 1:5 Dual Diff.
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
The MC100LVEP210 is a low skew 1–to–5 dual differential driver,
designed with clock distribution in mind. The LVECL/LVPECL input
signals can be either differential or single–ended if the VBB output is
used. The signal is fanned out to 5 identical differential outputs. HSTL
inputs can be used when the EP210 is operating in LVPECL mode.
The LVEP210 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device
and from lot to lot.
To ensure the tight skew specification is realized, both sides of the
differential output need to be terminated identically into 50Ω even if
only one side is being used. When fewer than all ten pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
The MC100LVEP210, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP210 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in PECL mode, or VEE ≤ –3.0V in ECL mode.
Designers can take advantage of the LVEP210’s performance to
distribute low skew clocks across the backplane or the board. In a
LVPECL environment, series or Thevenin line terminations are
typically used as they require no additional power supplies. For more
information on using PECL, designers should refer to Application
Note AN1406/D.
• 100ps Part–to–Part Skew
• 35ps Output–to–Output Skew
• Differential Design
• VBB Output
• 475ps Typical Propagation Delay
• High Bandwidth to 1.5GHz Typical
• LVPECL and HSTL mode: 2.375V to 3.8V VCC with VEE = 0V
• LVECL mode: 0V VCC with VEE = –2.375V to –3.8V
• Internal Input Resistors: Pulldown on D, D
• Pullup and Pulldown on CLK
• ESD Protection: >2KV HBM, >100V MM
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 461 devices
http://onsemi.com
32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC100
LVEP210
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
32
1
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package Shipping
MC100LVEP210FA TQFP 250 Units/Tray
MC100LVEP210FAR2 TQFP 2000 Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
March, 2000 – Rev. 2
Publication Order Number:
MC100LVEP210/D