MC100LVEP14 Datasheet, PDF (1/8 Pages) ON Semiconductor – Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

MC100LVEP14
Low-Voltage 1:5 Differential
LVECL/LVPECL/LVEPECL/HSTL
Clock Driver
The MC100LVEP14 is a low skew 1–to–5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The LVECL/LVPECL input signals can be either differential
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or single–ended (if the VBB output is used). HSTL inputs can be used
when the LVEP14 is operating under LVPECL conditions.
The LVEP14 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device and
20
from lot to lot.
To ensure that the tight skew specification is realized, both sides of
W any differential output need to be terminated identically into 50 even
if only one side is being used. When fewer than all five pairs are used,
identically terminate all the output pairs on the same package side
1
TSSOP–20
DT SUFFIX
CASE 948E
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
MARKING DIAGRAM*
margin (propagation delay) in the output(s) in use.
The common enable (EN) is synchronous, outputs are enabled/
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
100
VP14
ALYW
VP = LVEP
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
negative edge of the clock input.
The MC100LVEP14, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP14 to be used for high performance clock distribution in
*For additional information, see Application Note
AND8002/D
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in LVPECL mode, or VEE ≤ –3.0V in LVECL mode.
Designers can take advantage of the LVEP14’s performance to
ORDERING INFORMATION
distribute low skew clocks across the backplane or the board. For more
information, refer to Application Note AN1406/D.
Device
Package Shipping
• 100ps Part–to–Part Skew
MC100LVEP14DT TSSOP 75 Units/Tray
• 25ps Output–to–Output Skew
• Differential Design
MC100LVEP14DTR2 TSSOP 2500 Tape & Reel
• 400ps Typical Propagation Delay
• High Bandwidth to 1.5 Ghz Typical
• LVPECL and HSTL mode: +2.375V to +3.8V VCC with VEE = 0V
• LVECL mode: 0V VCC with VEE = –2.375V to –3.8V
• 75kΩ Internal Pulldown CLKs, Pull up & Pulldown CLKs
• ESD Protection: >2KV HBM; >100V MM
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
• Transistor Count = 357 devices
© Semiconductor Components Industries, LLC, 2000
1
May, 2000 – Rev. 1
Publication Order Number:
MC100LVEP14/D