MC100LVELT22_07 Datasheet, PDF (1/7 Pages) ON Semiconductor – 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

MC100LVELT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Low Voltage Positive ECL)
levels are used, only +3.3 V and ground are required. The small outline
8-lead package and the low skew, dual gate design of the LVELT22
makes it ideal for applications which require the translation of a clock
and a data signal.
Features
• 350 ps Typical Propagation Delay
• <100 ps Output−to−Output Skew
• Flow Through Pinouts
• The 100 Series Contains Temperature Compensation
• LVPECL Operating Range: V_CC = 3.0 V to 3.8 V
with GND = 0 V
• When Unused TTL Input is left Open, Q Output will Default High
• Pb−Free Packages are Available
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
KVT22
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
KR22
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
March, 2007 − Rev. 5
Publication Order Number:
MC100LVELT22/D