MC100LVELT22 Datasheet, PDF (1/3 Pages) ON Semiconductor – Dual LVTTL/LVCMOS to Differential LVPECL Translator

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual LVTTL/LVCMOS to
Differential LVPECL
Translator
The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL
translator. Because LVPECL (Low Voltage Positive ECL) levels are used,
only +3.3V and ground are required. The small outline 8-lead SOIC
package and the low skew, dual gate design of the LVELT22 makes it
ideal for applications which require the translation of a clock and a data
signal.
• 350ps Typical Propagation Delay
• <100ps Output–to–Output Skew
• Differential LVPECL Outputs
• Small Outline SOIC Package
• Flow Through Pinouts
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Q0 1
8 VCC
Q0 2
LVPECL
Q1 3
7 D0
LVTTL/
LVCMOS
6 D1
Q1 4
5 _GND
MC100LVELT22
8
1
D SUFFIX
8–LEAD PLASTIC SOIC PACKAGE
CASE 751-05
PIN DESCRIPTION
PIN
Qn
Dn
VCC
GND
FUNCTION
Diff PECL Outputs
LVTTL/LVCMOS Inputs
+3.3V Supply
Ground
12/96
© Motorola, Inc. 1996
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