MC100LVELT20 Datasheet, PDF (1/6 Pages) ON Semiconductor – 3.3V LVTTL/LVCMOS to Differential LVPECL Translator

MC100LVELT20
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3.3V LVTTL/LVCMOS to
Differential LVPECL
Translator
The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL
translator. Because PECL (Positive ECL) levels are used, only +3.3 V
and ground are required. The small outline SOIC−8 package and the
single gate of the MC100LVELT20 makes it ideal for those
applications where space, performance, and low power are at a
premium.
The 100 Series contains temperature compensation.
• 390 ps Typical Propagation Delay
• Maximum Input Clock Frequency > 0.8 GHz Typical
• Operating Range V_CC = 3.0 V to 3.6 V
with GND = 0 V
• PNP TTL Input for Minimal Loading
• Q Output will Default HIGH with Input Open
http://onsemi.com
8
1
SO−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
KVT20
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2004
1
September, 2004 − Rev. P1
Publication Order Number:
MC100LVELT20/D