MC100LVEL39_16 Datasheet, PDF (1/6 Pages) ON Semiconductor – 3.3V ECL Clock Generation Chip

MC100LVEL39
3.3 V ECL ÷2/4, ÷4/6 Clock
Generation Chip
Description
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
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output edges are all precisely aligned. The device can be driven by
either a differential or single-ended input signal. In addition, by using
the V_BB output, a sinusoidal source can be AC coupled into the device.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. An internal runt pulse could lead to losing
SOIC−20 WB
DW SUFFIX
CASE 751D
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
MARKING DIAGRAM*
clock input.
20
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple LVEL39s, the Master Reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one LVEL39, the MR pin need not be exercised as the
100LVEL39
AWLYYWWG
internal divider design ensures synchronization between the ÷2/4 and the
÷4/6 outputs of a single device.
1
The V_BB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to V_BB as a switching reference voltage. V_BB may also
rebias AC coupled inputs. When used, decouple V_BB and V_CC via
a .01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
not used, V_BB should be left open.
Features
*For additional marking information, refer to
Application Note AND8002/D.
• 50 ps Maximum Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
ORDERING INFORMATION
• ESD Protection: Human Body Model; > 2 kV
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
Device
Package
Shipping^†
MC100LVEL39DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
V_CC = 3.0 V to 3.8 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
♦ For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 419 devices
• These Devices are Pb-Free, Halogen Free and are
RoHS Compliant
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 11
Publication Order Number:
MC100LVEL39/D