MC100LVEL38_16 Datasheet, PDF (1/7 Pages) ON Semiconductor – 3.3V ECL Clock Generation Chip

MC100LVEL38
3.3 V ECL ÷2, ÷4/6 Clock
Generation Chip
Description
The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended input signal.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as can happen with an
asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to
a HIGH. This output allows for clock synchronization within the
system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2 and the ÷4/6 outputs of
a single device.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
www.onsemi.com
SOIC−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL38
AWLYYWWG
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Features
• 50 ps Maximum Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• ESD Protection: > 2 kV Human Body Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
V_CC = 3.0 V to 3.8 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −3.8 V
• Internal Input 75 kW Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
• Moisture Sensitivity: Level 3 (Pb-Free)
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 388 devices
• These Devices are Pb-Free, Halogen Free and are
RoHS Compliant
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 11
Publication Order Number:
MC100LVEL38/D