MC100LVEL38 Datasheet, PDF (1/5 Pages) ON Semiconductor – ÷2, ÷4/6 Clock Generation Chip

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
÷2, ÷4/6 Clock Generation Chip
The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but
is specified for operation at the standard 100K ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPS™ Data Book DL140/D). If a single-ended input is
to be used, the VBB output should be connected to the CLK input and
bypassed to ground via a 0.01µF capacitor. The VBB output is designed to
act as the switching reference for the input of the LVEL38 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever the
÷2 and the ÷4/6 outputs are both transitioning from a LOW to a HIGH.
This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2 and the ÷4/6 outputs of a
single device.
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >1500V ESD Protection
• Low Voltage VEE Range of –3.0 to –3.8V
Pinout: 20-Lead SOIC (Top View)
VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
VCC EN DIV_SEL CLK CLK VBB MR VCC
MC100LVEL38
MC100EL38
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
PIN
FUNCTION
CLK
EN
MR
VBB
Q0, Q1
Q2, Q3
DIVSEL
Phase_Out
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff ÷2 Outputs
Diff ÷4/6 Outputs
Frequency Select Input
Phase Sync Signal
CLK
FUNCTION TABLE
EN
MR FUNCTION
Z
L
L
ZZ
H
L
X
X
H
Z = Low-to-High Transition
ZZ = High-to-Low Transition
Divide
Hold Q0–3
Reset Q0–3
DIVSEL
0
1
Q2, Q3 OUTPUTS
Divide by 4
Divide by 6
10/94
© Motorola, Inc. 1996
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