MC100LVEL31_06 Datasheet, PDF (1/8 Pages) ON Semiconductor – 3.3V ECL D Flip-Flop with Set and Reset

MC100LVEL31
3.3V ECL D Flip-Flop
with Set and Reset
Description
The MC100LVEL31 is a D flip-flop with set and reset. The device is
functionally equivalent to the EL31 device but operates from a 3.3 V
supply. With propagation delays and output transition times essentially
equivalent to the EL31, the LVEL31 is ideally suited for those
applications which require the ultimate in AC performance at low power
supply voltages.
Both set and reset inputs are asynchronous, level triggered signals.
Data enters the master portion of the flip-flop when clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock.
Features
• 475 ps Typical Propagation Delay
• 2.9 GHz Toggle Frequency
• ESD Protection: >4 kV Human Body Model,
>200 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V_CC = 3.0 V to 3.8 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 121 devices
• Pb−Free Packages are Available
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
KVL31
ALYW
G
1
8
KV31
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 3
Publication Order Number:
MC100LVEL31/D