MC100LVEL30_16 Datasheet, PDF (1/6 Pages) ON Semiconductor – ECL Triple D Flip‐Flop with Set and Reset

MC100LVEL30
3.3 V ECL Triple D Flip‐Flop
with Set and Reset
Description
The MC100LVEL30 is a triple master-slave D flip-flop with
differential outputs. Data enters the master latch when the clock input
is LOW and transfers to the slave upon a positive transition on the
clock input.
In addition to a common Set input individual Reset inputs are
provided for each flip-flop. Both the Set and Reset inputs function
asynchronous and overriding with respect to the clock inputs.
Features
• 1200 MHz Minimum Toggle Frequency
• 450 ps Typical Propagation Delays
• ESD Protection: > 2 kV Human Body Model
• The 100 Series Contains Temperature Compensation.
• PECL Mode Operating Range:
V_CC = 3.0 V to 3.8 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −3.8 V
• Internal Input 75 kW Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 347 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
SOIC−20 WB
DW SUFFIX
CASE 751D−05
MARKING DIAGRAM*
20
100LVEL30
AWLYYWWG
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping†
MC100LVEL30DWG
SOIC−20 WB 38 Units / Tube
(Pb-Free)
MC100LVEL30DWR2G SOIC−20 WB 1000 Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 8
Publication Order Number:
MC100LVEL30/D