MC100LVEL29_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – 3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

MC100LVEL29
3.3V ECL Dual Differential
Data and Clock D Flip−Flop
With Set and Reset
Description
The MC100LVEL29 is a dual master−slave flip flop. The device
features fully differential Data and Clock inputs as well as outputs.
The MC100LVEL29 is pin and functionally equivalent to the
MC100EL29. Data enters the master latch when the clock is LOW and
transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to V_EE and the D input will
bias around V_CC/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
Features
• 1100 MHz Flip−Flop Toggle Frequency
• ESD Protection: >2 kV Human Body Model
• 580 ps Typical Propagation Delays
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V_CC = 3.0 V to 3.8 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 313 devices
• Pb−Free Packages are Available*
http://onsemi.com
SO−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL29
AWLYYWWG
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 5
Publication Order Number:
MC100LVEL29/D