MC100LVEL05_06 Datasheet, PDF (1/8 Pages) ON Semiconductor – 3.3V ECL 2-Input Differential AND/NAND

MC100LVEL05
3.3V ECL 2-Input Differential
AND/NAND
Description
The MC100LVEL05 is a 2-input differential AND/NAND gate. The
device is functionally equivalent to the MC100EL05 device and
operates from a 3.3 V supply voltage. With propagation delays and
output transition times equivalent to the EL05, the LVEL05 is ideally
suited for those applications which require the ultimate in AC
performance at low voltage power supplies.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the
LVEL05 to also be used as a 2-input differential OR/NOR gate.
Features
• 340 ps Propagation Delay
• High Bandwidth Output Transitions
• ESD Protection: >4 kV Human Body Model,
>200 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V_CC = 3.0 V to 3.8 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with All Inputs Open or at V_EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 69 devices
• Pb−Free Packages are Available
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
KVL05
ALYW
G
1
8
KV05
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 3
Publication Order Number:
MC100LVEL05/D