MC100EPT622_06 Datasheet, PDF (1/7 Pages) ON Semiconductor – 3.3V LVTTL/LVCMOS to LVPECL Translator

MC100EPT622
3.3V LVTTL/LVCMOS to
LVPECL Translator
The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The device has an OR−ed enable input which
can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
(ENTTL). If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel−to−channel skew
Features
• 450 ps Typical Propagation Delay
• Maximum Frequency > 1.5 GHz Typical
• PECL Mode
• Operating Range: V_CC = 3.0 V to 3.8 V with V_EE = 0 V
• PNP LVTTL Inputs for Minimal Loading
• Q Output Will Default HIGH with Inputs Open
• The 100 Series Contains Temperature Compensation.
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAM*
LQFP−32
FA SUFFIX
CASE 873A
MC100
EPT622
AWLYYWW
32
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
Table 1. TRUTH TABLE
ENPECL ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 4
Publication Order Number:
MC100EPT622/D