MC100EPT622 Datasheet, PDF (1/8 Pages) ON Semiconductor – 3.3V LVTTL/LVCMOS to LVPECL Translator

MC100EPT622
3.3V LVTTL/LVCMOS to
LVPECL Translator
The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The device has an OR- ed enable input which
can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
(ENTTL). If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel- to- channel skew
• 450 ps Typical Propagation Delay
• Maximum Frequency > 1.5 GHz Typical
• PECL Mode
• Operating Range: V_CC = 3.0 V to 3.8 V with V_EE = 0 V
• PNP LVTTL Inputs for Minimal Loading
• Q Output Will Default HIGH with Inputs Open
• The 100 Series Contains Temperature Compensation.
ENPECL
ENTTL
D0
Q0
D1
Q1
D2
Q2
D3
Q3
LVCMOS/TTL D4
Q4 LVPECL
D5
Q5
D6
Q6
D7
Q7
D8
Q8
D9
Q9
Figure 1. Logic Symbol
http://onsemi.com
MARKING
DIAGRAM*
LQFP-32
FA SUFFIX
CASE 873A
MC100
EPT622
AWLYYWW
32
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package
MC100EPT622FA LQFP32
Shipping
250 Unit Trays
MC100EPT622FAR2 LQFP32 2000 Tape & Reel
TRUTH TABLE
ENPECL ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
© Semiconductor Components Industries, LLC, 2002
1
December, 2002 - Rev. 2
Publication Order Number:
MC100EPT622/D