MC100EPT26_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – 3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

MC100EPT26
3.3V 1:2 Fanout Differential
LVPECL/LVDS to LVTTL
Translator
Description
The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are
used only +3.3 V and ground are required. The small outline 8−lead
package and the 1:2 fanout design of the EPT26 makes it ideal for
applications which require the low skew duplication of a signal in a
tightly packed PC board.
The V_BB output allows the EPT26 to be used in a single−ended input
mode. In this mode the V_BB output is tied to the D0 input for a
non−inverting buffer or the D0 input for an inverting buffer. If used,
the V_BB pin should be bypassed to ground with > 0.01 mF capacitor.
For a single−ended direct connection, use an external voltage
reference source such as a resistor divider. Do not use V_BB for a
single−ended direct connection or port to another device.
Features
• 1.4 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• The 100 Series Contains Temperature Compensation
• Operating Range: V_CC = 3.0 V to 3.6 V with GND = 0 V
• 24 mA TTL outputs
• Q Outputs Will Default LOW with Inputs Open or at V_EE
• V_BB Output
• Pb−Free Packages are Available
http://onsemi.com
8
1
8
1
SO−8
D SUFFIX
CASE 751
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
KPT26
ALYW
G
1
8
KA26
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
1
3W MG
G
4
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 14
Publication Order Number:
MC100EPT26/D