MC100EPT26 Datasheet, PDF (1/4 Pages) ON Semiconductor – 1:2 Fanout Differential LVPECL to LVTTL Translator

MC100EPT26
1:2 Fanout Differential
LVPECL to LVTTL
Translator
The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL
translator. Because LVPECL (Positive ECL) levels are used only
+3.3V and ground are required. The small outline 8–lead SOIC
package and the 1:2 fanout design of the EPT26 makes it ideal for
applications which require the low skew duplication of a signal in a
tightly packed PC board.
The VBB output allows the EPT26 to be used in a single–ended
input mode. In this mode the VBB output is tied to the D0 input for a
non–inverting buffer or the D0 input for an inverting buffer. If used,
the VBB pin should be bypassed to ground via a 0.01µF capacitator.
• 1.4ns Typical Propagation Delay
• 275MHz Fmax (Clock bit stream, not pseudo–random)
• Differential LVPECL inputs
• Small Outline SOIC Package
• 24mA TTL outputs
• Flowthrough Pinouts
• ESD Protection: >2KV HBM, >100V MM
• Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
• Q Outputs will default LOW with inputs open or at VEE
• VBB Output
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 117 devices
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING
DIAGRAMS*
8
HPT26
ALYW
1
8
1
TSSOP–8
DT SUFFIX
CASE 948R
8
HR26
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
PIN
Q0, Q1
D, D
VCC
VBB
GND
PIN DESCRIPTION
FUNCTION
LVTTL Outputs
Differential LVPECL Input Pair
Positive Supply
Reference Voltage
Ground
NC 1
D2
D3
8 VCC
7 Q0
LVTTL
6 Q1
VBB 4 LVPECL
5 GND
ORDERING INFORMATION
Device
Package
Shipping
MC100EPT26D
SO–8
98 Units / Rail
MC100EPT26DR2
SO–8
2500 / Reel
MC100EPT26DT TSSOP–8 98 Units / Rail
MC100EPT26DTR2 TSSOP–8 2500 / Reel
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
© Semiconductor Components Industries, LLC, 2000
1
May, 2000 – Rev. 2
Publication Order Number:
MC100EPT26/D