MC100EPT24 Datasheet, PDF (1/4 Pages) ON Semiconductor – LVTTL/LVCOMS to Differential LVECL Translator

MC100EPT24
LVTTL/LVCMOS to Differential
LVECL Translator
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a –3.3V, +3.3V and ground are required. The small outline
8–lead SOIC package and the single gate of the EPT24 makes it ideal
for those applications where space, performance, and low power are at
a premium.
The EPT24 is available in the 100E standard and is compatible with
ECL 100K logic levels.
• 350ps Typical Propagation Delay
• Maximum Frequency > 1.0GHz
• Differential ECL Outputs
• Small Outline SOIC Package
• PNP LVTTL Inputs for Minimal Loading
• Flow Through Pinouts
• Q Output will default HIGH with inputs open
• ESD Protection: 4000 KV HBM, 200 V MM
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 181 devices
VEE 1
LVTTL
D2
8 VCC
7Q
LVECL
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
KPT24
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
PIN
Q, Q
D
VCC
GND
VEE
PIN DESCRIPTION
FUNCTION
Differential LVECL Outputs
LVTTL Input
Positive Supply
Ground
Negative Supply
NC 3
6Q
NC 4
5 GND
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
ORDERING INFORMATION
Device
Package
Shipping
MC100EPT24D
SOIC
98 Units/Rail
MC100EPT24DR2 SOIC 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 1
Publication Order Number:
MC100EPT24/D