MC100EPT22 Datasheet, PDF (1/4 Pages) ON Semiconductor – Dual LVTTL/LVCMOS to Differential LVPECL Translator

MC100EPT22
Dual LVTTL/LVCMOS to
Differential LVPECL Translator
The MC100EPT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Positive ECL) levels are used
only +3.3V and ground are required. The small outline 8–lead SOIC
package and the single gate of the EPT22 makes it ideal for those
applications where space, performance, and low power are at a
premium. Because the mature MOSAIC 5 process is used, low cost
and high speed can be added to the list of features.
• 420ps Typical Propagation Delay
• Differential LVPECL Outputs
• Small Outline SOIC Package
• PNP LVTTL Inputs for Minimal Loading
• Flow Through Pinouts
• Q Output will default HIGH with inputs open
• ESD Protection: 4.0 KV HBM, 200 V MM
• Maximum Frequency > 1.1 GHz
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 164 devices
http://onsemi.com
8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
KPT22
ALYW
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
1
*For additional information, see Application Note
AND8002/D
Q0 1
8 VCC
Q0 2
LVPECL
Q1 3
7 D0
LVTTL
6 D1
PIN DESCRIPTION
PIN
FUNCTION
Q0, Q1, Q0, Q1
Diff. LVPECL Outputs
D0, D1
LVTTL Inputs
VCC
GND
Positive Supply
Ground
Q1 4
5 GND
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
ORDERING INFORMATION
Device
Package
Shipping
MC100EPT22D
SOIC
98 Units/Rail
MC100EPT22DR2 SOIC 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 1999
1
September, 1999 – Rev. 2.0
Publication Order Number:
MC100EPT22/D