MC100EP809_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

MC100EP809
3.3V 1:9 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Enable
Description
The MC100EP809 is a low skew 1−to−9 differential clock driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or PECL and they are selected by the CLK_SEL pin
which is LVTTL. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE), which is LVTTL, is
synchronous ensuring the outputs will only be enabled/disabled when they
are already in LOW state (Figure 8).
The MC100EP809 guarantees low output−to−output skew. The optimal
design, layout, and processing minimize skew within a device and from lot
to lot. The MC100EP809 output structure uses open emitter architecture
and will be terminated with 50 W to ground instead of a standard HSTL
configuration (Figure 6). To ensure the tight skew specification is realized,
both sides of the differential output need to be terminated identically into
50 W even if only one output is being used. If an output pair is unused,
both outputs may be left open (unterminated) without affecting skew.
Designers can take advantage of the EP809’s performance to
distribute low skew clocks across the backplane of the board. HSTL
clock inputs may be driven single−end by biasing the non−driven pin
in an input pair (Figure 7).
Features
• 100 ps Typical Device−to−Device Skew
• 15 ps Typical within Device Skew
• HSTL Compatible Outputs Drive 50 W to GND with no
Offset Voltage
• Maximum Frequency > 750 MHz
• 850 ps Typical Propagation Delay
• Fully Compatible with Micrel SY89809L
• PECL and HSTL Mode Operating Range: V_CCI = 3 V to 3.6 V
with GND = 0 V, V_CCO = 1.6 V to 2.0 V
• Open Input Default State
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAM*
32−LEAD LQFP
FA SUFFIX
CASE 873A
MC100
EP809
AWLYYWWG
32
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 7
Publication Order Number:
MC100EP809/D