MC100EP32 Datasheet, PDF (1/10 Pages) ON Semiconductor – 3.3V 5V ECL / 2 Divider

MC10EP32, MC100EP32
3.3V / 5V ECL B2 Divider
The MC10/100EP32 is an integrated B2 divider with differential
CLK inputs.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power−up, the internal flip−flops will attain a random state; the
reset allows for the synchronization of multiple EP32’s in a system.
The 100 Series contains temperature compensation.
• 350 ps Typical Propagation Delay
• Maximum Frequency > 4 GHz Typical (Figure 3)
• PECL Mode Operating Range:
V_CC = 3.0 V to 5.5 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V_EE
• Pb−Free Package is Available
http://onsemi.com
MARKING DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
HEP32
ALYW
1
8
KEP32
ALYW
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
HP32
ALYW
1
8
KP32
ALYW
1
H = MC10
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2004
1
June, 2004 − Rev. 7
Publication Order Number:
MC10EP32/D