MC100EP210S_11 Datasheet, PDF (1/8 Pages) ON Semiconductor – 1:5 Dual Differential LVDS Compatible Clock Driver

MC100EP210S
2.5V 1:5 Dual Differential
LVDS Compatible Clock
Driver
Description
The MC100EP210S is a low skew 1−to−5 dual differential driver,
designed with LVDS clock distribution in mind. The LVDS or
LVPECL input signals are differential and the signal is fanned out to
five identical differential LVDS outputs.
The EP210S specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
Two internal 50 W resistors are provided across the inputs. For
LVDS inputs, VTA and VTB pins should be unconnected. For
LVPECL inputs, VTA and VTB pins should be connected to the V_TT
(V_CC − 2.0 V) supply.
Designers can take advantage of the EP210S performance to
distribute low skew LVDS clocks across the backplane or the board.
Features
• 20 ps Typical Output−to−Output Skew
• 85 ps Typical Device−to−Device Skew
• 550 ps Typical Propagation Delay
• The 100 Series Contains Temperature Compensation
• Maximum Frequency > 1 GHz Typical
• Operating Range: V_CC = 2.375 V to 2.625 V with V_EE = 0 V
• Internal 50 W Input Termination Resistors
• LVDS Input/Output Compatible
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM*
LQFP−32
FA SUFFIX
CASE 873A
MC100
EP210S
AWLYYWWG
1 32
QFN32
MN SUFFIX
CASE 488AM
1
MCxxx
EP210S
ALYWG
xxx = 10 or 100
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
June, 2011 − Rev. 10
Publication Order Number:
MC100EP210S/D