MC100EP196_14 Datasheet, PDF (1/19 Pages) ON Semiconductor – 3.3V ECL Programmable Delay Chip with FTUNE

MC100EP196
3.3V ECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
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delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V_CC to V_EE to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
MARKING
DIAGRAM*
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
LEN allows a transparent LOAD mode of real time delay values by
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
LQFP−32
MC100
EP196
AWLYYWWG
current values present against any subsequent changes in D[10:0]. The
approximate delay values for varying tap numbers correlating to D0 (LSB)
FA SUFFIX
32
CASE 873A
through D9 (MSB) are shown in Table 5.
1
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
A
= Assembly Location
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
*For additional marking information, refer to
Application Note AND8002/D.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between V_EF (pin 7) and V_CF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
operation is available in PECL mode only. For LVCMOS input levels,
leave V_CF and V_EF open. For ECL operation, short V_CF and V_EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
reference to V_CF and leave open V_EF pin. The 1.5 V reference voltage
to V_CF pin can be accomplished by placing a 2.2 kW resistor between
V_CF and V_EE for 3.3 V power supply.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The 100 Series contains temperature compensation.
• Maximum Frequency > 1.2 GHz Typical
• Open Input Default State
• Programmable Range: 0 ns to 10 ns
• Safety Clamp on Inputs
• Delay Range: 2.4 ns to 12.4 ns
• A Logic High on the EN Pin Will Force Q to Logic
• 10 ps Increments
• PECL Mode Operating Range:
Low
• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
V_CC = 3.0 V to 3.6 V with V_EE = 0 V
• NECL Mode Operating Range:
V_CC = 0 V with V_EE = −3.0 V to −3.6 V
Inputs
• V_BB Output Reference Voltage
• These are Pb−Free Devices*
© Semiconductor Components Industries, LLC,2014
1
June, 2014 − Rev. 16
Publication Order Number:
MC100EP196/D