MC100EP16VC_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output

MC100EP16VC
3.3V / 5V ECL Differential
Receiver/Driver with High
Gain and Enable Output
Description
The EP16VC is a differential receiver/driver. The device is
functionally equivalent to the EP16 and LVEP16 devices but with high
gain and enable output.
The EP16VC provides an EN input which is synchronized with the
data input (D) signal in a way that provides glitchless gating of the
QHG and QHG outputs.
When the EN signal is LOW, the input is passed to the outputs and
the data output equals the data input. When the data input is HIGH and
EN goes HIGH, it will force the Q_HG LOW and the Q_HG HIGH on the
next negative transition of the data input. If the data input is LOW
when the EN goes HIGH, the next data transition to a HIGH is ignored
and Q_HG remains LOW and Q_HG remains HIGH. The next positive
transition of the data input is not passed on to the data outputs under
these conditions. The Q_HG and Q_HG outputs remain in their disabled
state as long as the EN input is held HIGH. The EN input has no
influence on the Q output and the data input is passed on (inverted) to
this output whether EN is HIGH or LOW. This configuration is ideal
for crystal oscillator applications where the oscillator can be free
running and gated on and off synchronously without adding extra
counts to the output.
The V_BB/D pin is internally dedicated and available for differential
interconnect. V_BB/D may rebias AC coupled inputs. When used,
decouple V_BB/D and V_CC via a 0.01 mF capacitor and limit current
sourcing or sinking to 1.5 mA. When not used, V_BB/D should be left
open.
The 100 Series contains temperature compensation.
Features
• 310 ps Typical Prop Delay Q,
380 ps Typical Prop Delay QHG, QHG
• Gain > 200
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: V_CC = 3.0 V to 5.5 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −3.0 V to −5.5 V
• Open Input Default State
• Q_HG Output Will Default LOW with D Inputs Open or at V_EE
• V_BB Output
• Pb−Free Packages are Available
http://onsemi.com
8
1
MARKING DIAGRAMS*
SOIC−8
D SUFFIX
CASE 751
8
KEP66
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
8
KP66
ALYWG
G
1
DFN8
MN SUFFIX
CASE 506AA
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
December, 2006 − Rev. 5
Publication Order Number:
MC10EP16VC/D