MC100ELT23 Datasheet, PDF (1/3 Pages) ON Semiconductor – Dual Differential PECL to TTL Translator

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Differential PECL to
TTL Translator
The MC100ELT23 is a dual differential PECL to TTL translator.
Because PECL (Positive ECL) levels are used only +5V and ground are
required. The small outline 8-lead SOIC package and the dual gate
design of the ELT23 makes it ideal for applications which require the
translation of a clock and a data signal. Because the mature MOSAIC 1.5
process is used, low cost can be added to the list of features.
The ELT23 is available in only the ECL 100K standard. Since there are
no PECL outputs or an external VBB reference, the ELT23 does not
require both ECL standard versions. The PECL inputs are differential;
there is no specified difference between the differential input 10H and
100K standards. Therefore, the MC100ELT23 can accept any standard
differential PECL input referenced from a VCC of 5.0V.
• 3.5ns Typical Propagation Delay
• Differential PECL Inputs
• Small Outline SOIC Package
• 24mA TTL Outputs
• Flow Through Pinouts
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D0 1
D0 2
PECL
D1 3
8 VCC
7 Q0
TTL
6 Q1
D1 ⁴
5 _GND
MC100ELT23
8
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
PIN DESCRIPTION
PIN
Qn
Dn
VCC
GND
FUNCTION
TTL Outputs
Diff PECL Inputs
+5.0V Supply
Ground
7/96
© Motorola, Inc. 1996
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