MC100EL38 Datasheet, PDF (1/6 Pages) ON Semiconductor – 5V ECL Clock Generation Chip

MC100EL38
5 V ECL ÷2, ÷4/6 Clock
Generation Chip
Description
The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
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either a differential or single-ended ECL or, if positive power supplies
are used, PECL input signal.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The common enable (EN) is synchronous so that the internal
SOIC−20 WB
DW SUFFIX
CASE 751D−05
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
MARKING DIAGRAM*
20
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
100EL38
stages. The internal enable flip-flop is clocked on the falling edge of
AWLYYWWG
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
The Phase_Out output will go HIGH for one clock cycle whenever
1
the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a
HIGH. This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple EL38s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
which only use one EL38, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2 and
*For additional marking information, refer to
Application Note AND8002/D.
the ÷4/6 outputs of a single device.
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
ORDERING INFORMATION
• Master Reset for Synchronization
Device
Package
Shipping^†
• ESD Protection:
♦ 2 kV Human Body Model
MC100EL38DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
♦ 100 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
♦ V_CC = 4.2 V to 5.7 V with V_EE = 0 V
• NECL Mode Operating Range:
• Moisture Sensitivity Level: 3 (Pb-Free)
♦ V_CC = 0 V with V_EE = −4.2 V to −5.7 V
• Internal 75 kW Input Pulldown Resistors on CLK, EN,
MR, and DIVSEL
♦ For Additional Information, see Application Note
AND8003/D
• Flammability Rating:
• Q Output will Default LOW with Inputs Open or at
V_EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
♦ UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 388 devices
• These Devices are Pb-Free, Halogen Free and are
Latchup Test
RoHS Compliant
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 9
Publication Order Number:
MC100EL38/D