MC100E310_16 Datasheet, PDF (1/8 Pages) ON Semiconductor – 5 V ECL Low Voltage 2:8 Differential Fanout Buffer

MC100E310
5 V ECL Low Voltage 2:8
Differential Fanout Buffer
Description
The MC100E310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The E310 offers two selectable clock inputs to allow for
redundant or test clocks to be incorporated into the system clock trees.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10−20 ps increase in TPD, so the
relative skew between any two output pairs remains about 25 ns.
For more information on using PECL, designers should refer to
ON Semiconductor Application Note AN1406/D.
The V_BB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V_BB as a switching reference voltage.
V_BB may also rebias AC coupled inputs. When used, decouple V_BB
and V_CC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V_BB should be left open.
The 100 Series Contains Temperature Compensation.
Features
• Dual Differential Fanout Buffers
• 200 ps Part-to-Part Skew
• 50 ps Output-to-Output Skew
• 28-lead PLCC Packaging
• Q Output will Default LOW with Inputs Open or at V_EE
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V
with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V
with V_EE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
♦ > 2 kV Human Body Model
♦ > 200 V Machine Model
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 212 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
PLCC−28
FN SUFFIX
CASE 776−02
MARKING DIAGRAM*
1 28
MC100E310FNG
AWLYYWW
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping†
MC100E310FNG
PLCC−28 37 Units / Tube
(Pb-Free)
MC100E310FNR2G
PLCC−28 500 Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 7
Publication Order Number:
MC100E310/D