MC100E210 Datasheet, PDF (1/8 Pages) ON Semiconductor – 5V ECL Dual 1:4, 1:5 Differential Fanout Buffer

MC100E210
5V ECL Dual 1:4, 1:5
Differential Fanout Buffer
The MC100E210 is a low voltage, low skew dual differential ECL
fanout buffer designed with clock distribution in mind. The device
features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The
device features fully differential clock paths to minimize both device and
system skew. The dual buffer allows for the fanout of two signals through
a single chip, thus reducing the skew between the two fundamental
signals from a part−to−part skew down to an output−to−output skew. This
capability reduces the skew by a factor of 4 as compared to using two
LVE111’s to accomplish the same task.
The lowest TPD delay time results from terminating only one output
pair, and the greatest TPD delay time results from terminating all the
output pairs. This shift is about 10−20 pS in TPD. The skew between
any two output pairs within a device is typically about 25 nS. If other
output pairs are not terminated, the lowest TPD delay time results
from both output pairs and the skew is typically 25 nS. When all
outputs are terminated, the greatest TPD (delay time) occurs and all
outputs display about the same 10−20 pS increase in TPD, so the
relative skew between any two output pairs remains about 25 nS.
For more information on using PECL, designers should refer to
Application Note AN1406/D.
The V_BB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to V_BB as a switching reference voltage. V_BB may also
rebias AC coupled inputs. When used, decouple V_BB and V_CC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, V_BB should be left open.
• Dual Differential Fanout Buffers
• 200 ps Part−to−Part Skew
• 50 ps Typical Output−to−Output Skew
• Low Voltage ECL/PECL Compatible
• The 100 Series Contains Temperature Compensation
• 28−lead PLCC Packaging
• PECL Mode Operating Range: V_CC = 4.2 V to 5.7 V with V_EE = 0 V
• NECL Mode Operating Range: V_CC = 0 V with V_EE = −4.2 V to −5.7 V
• Internal Input 75 KW Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V_EE
• ESD Protection: Human Body Model; >2 KV,
Machine Model; >200 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 179 devices
http://onsemi.com
MARKING
DIAGRAM
1 28
PLCC−28
FN SUFFIX
CASE 776
MC100E210FN
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
Package Shipping^†
MC100E210FN
PLCC−28 37 Units / Rail
MC100E210FNR2 PLCC−28 500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
1
October, 2003 − Rev. 2
Publication Order Number:
MC100E210/D