DTC144TT1_05 Datasheet, PDF (1/4 Pages) ON Semiconductor – Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

DTC144TT1
Preferred Devices
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the SC−59
package which is designed for low power surface mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Moisture Sensitivity Level: 1
• ESD Rating: Human Body Model: Class 1
ESD Rating Machine Model: Class B
• The SC−59 package can be soldered using wave or reflow. The
modified gull−winged leads absorb thermal stress during soldering
eliminating the possibility of damage to the die.
• Pb−Free Package is Available
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
V_CBO
V_CEO
I_C
50
Vdc
50
Vdc
100
mAdc
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation
T_A = 25°C
Derate above 25°C
P_D
230 (Note 1) mW
338 (Note 2)
1.8 (Note 1) °C/W
2.7 (Note 2)
Thermal Resistance,
Junction-to-Ambient
R_qJA
540 (Note 1) °C/W
370 (Note 2)
Thermal Resistance,
Junction-to-Lead
R_qJL
264 (Note 1) °C/W
287 (Note 2)
Junction and Storage Temperature
Range
T_J, T_stg −55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
© Semiconductor Components Industries, LLC, 2005
1
October, 2005 − Rev. 2
http://onsemi.com
NPN SILICON BIAS
RESISTOR TRANSISTOR
PIN 2
R₁
BASE
(INPUT)
R₂
PIN 3
COLLECTOR
(OUTPUT)
PIN 1
EMITTER
(GROUND)
3
1
2
SC−59
CASE 318D
STYLE 1
MARKING DIAGRAM
8T M G
G
1
8T = Specific Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
DTC144TT1/D