DTA114EET1_06 Datasheet, PDF (1/13 Pages) ON Semiconductor – Bias Resistor Transistors

DTA114EET1 Series
Preferred Devices
Bias Resistor Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space. The device is housed in
the SC−75/SOT−416 package which is designed for low power
surface mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SC−75/SOT−416 package can be soldered using wave or reflow.
The modified gull−winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
• Pb−Free Packages are Available
MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)
Rating
Symbol Value
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
THERMAL CHARACTERISTICS
V_CBO
50
V_CEO
50
I_C
100
Rating
Symbol Value
Total Device Dissipation, FR−4 Board
(Note 1) @ T_A = 25°C
Derate above 25°C
P_D
200
1.6
Thermal Resistance, Junction−to−Ambient R_qJA
600
(Note 1)
Unit
Vdc
Vdc
mAdc
Unit
mW
mW/°C
°C/W
Total Device Dissipation, FR−4 Board
(Note 2) @ T_A = 25°C
Derate above 25°C
Thermal Resistance, Junction−to−Ambient
(Note 2)
P_D
R_qJA
300
mW
2.4 mW/°C
400 °C/W
Junction and Storage Temperature Range T_J, T_stg −55 to
°C
+150
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 × 1.0 Inch Pad.
http://onsemi.com
PNP SILICON BIAS
RESISTOR TRANSISTORS
PIN 1
R1
BASE
(INPUT) _R2
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
2
1
SC−75 (SOT−416)
CASE 463
STYLE 1
MARKING DIAGRAM
xx M G
G
xx
= Specific Device Code
xx = (Refer to page 2)
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
1
March, 2006 − Rev. 6
Publication Order Number:
DTA114EET1/D