CS5155 Datasheet, PDF (1/18 Pages) Cherry Semiconductor Corporation – CPU 5-Bit Synchronous Buck Controller

CS5155
CPU 5−Bit Synchronous
Buck Controller
The CS5155 is a 5−bit synchronous dual N−Channel buck
controller. It is designed to provide unprecedented transient response
for today’s demanding high−density, high−speed logic. The regulator
operates using a proprietary control method, which allows a 100 ns
response time to load transients. The CS5155 is designed to operate
over a 4.25−14 V range (V_CC) using 12 V to power the IC and 5.0 V as
the main supply for conversion.
The CS5155 is specifically designed to power Pentium® II
processors and other high performance core logic. It includes the
following features: on board, 5−bit DAC, short circuit protection,
1.0% output tolerance, V_CC monitor, and programmable Soft Start
capability. The CS5155 is backwards compatible with the 4−bit
CS5150, allowing the mother board designer the capability of using
either the CS5150 or the CS5155 with no change in layout. The
CS5155 is available in 16 pin surface mount and DIP packages.
Features
• Dual N−Channel Design
• Excess of 1.0 MHz Operation
• 100 ns Transient Response
• 5−Bit DAC
• Backward Compatible with 4−Bit CS5150/CS5151
• 30 ns Gate Rise/Fall Times
• 1.0% DAC Accuracy
• 5.0 V & 12 V Operation
• Remote Sense
• Programmable Soft Start
• Lossless Short Circuit Protection
• V_CC Monitor
• 25 ns FET Nonoverlap Time
• Adaptive Voltage Positioning
• V²â„¢ Control Topology
• Current Sharing
• Overvoltage Protection
http://onsemi.com
MARKING
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
16
CS5155
AWLYWW
1
16
1
DIP−16
N SUFFIX
CASE 648
16
CS5155
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
V_ID0
V_ID1
V_ID2
V_ID3
SS
V_ID4
C_OFF
V_FFB
V_FB
COMP
LGND
V_CC1
V_GATE(L)
PGND
V_GATE(H)
V_CC2
ORDERING INFORMATION
Device
Package
Shipping
CS5155GD16
CS5155GDR16
CS5155GN16
SO−16
SO−16
DIP−16
48 Units/Rail
2500 Tape & Reel
25 Units/Rail
© Semiconductor Components Industries, LLC, 2006
1
July, 2006 − Rev. 4
Publication Order Number:
CS5155/D