CS51311 Datasheet, PDF (1/21 Pages) Cherry Semiconductor Corporation – Synchronous CPU Buck Controller for 12V and 5V Applications

CS51311
Synchronous CPU
Buck Controller for 12 V
and 5.0 V Applications
The CS51311 is a synchronous dual NFET Buck Regulator
Controller. It is designed to power the core logic of the latest high
performance CPUs. It uses the V²â„¢ control method to achieve the
fastest possible transient response and best overall regulation. It
incorporates many additional features required to ensure the proper
operation and protection of the CPU and Power system. The CS51311
provides the industry’s most highly integrated solution, minimizing
external component count, total solution size, and cost.
The CS51311 is specifically designed to power Intel’s Pentium® II
processor and includes the following features: 5−bit DAC with 1.2%
tolerance, Power Good output, overcurrent hiccup mode protection,
V_CC monitor, soft start, adaptive voltage positioning, adaptive FET
non−overlap time, and remote sense. The CS51311 will operate over
an 8.4 V to 14 V range and is available in 14 lead narrow body surface
mount package.
Features
• Synchronous Switching Regulator Controller for CPU V_CORE
• Dual N−Channel MOSFET Synchronous Buck Design
• V² Control Topology
• 200 ns Transient Loop Response
• 5−Bit DAC with 1.2% Tolerance
• Hiccup Mode Overcurrent Protection
• 40 ns Gate Rise and Fall Times (3.3 nF Load)
• 65 ns Adaptive FET Non−Overlap Time
• Adaptive Voltage Positioning
• Power Good Output Monitors Regulator Output
• V_CC Monitor Provides Undervoltage Lockout
• Enable Through Use of the COMP Pin
http://onsemi.com
14
1
SO−14
D SUFFIX
CASE 751A
MARKING DIAGRAM
14
CS51311
AWLYWW
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
V_ID0
V_ID1
V_ID2
V_ID3
V_ID4
V_FB
V_OUT
14
COMP
C_OFF
PWRGD
GATE(L)
GND
GATE(H)
V_CC
ORDERING INFORMATION
Device
Package
Shipping
CS51311GD14
SO−14
55 Units/Rail
CS51311GDR14
SO−14 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
1
July, 2006 − Rev. 3
Publication Order Number:
CS51311/D