CAV25128 Datasheet, PDF (1/13 Pages) ON Semiconductor – SPI Serial CMOS EEPROM

CAV25128
128-Kb SPI Serial CMOS
EEPROM
Description
The CAV25128 is a 128−Kb Serial CMOS EEPROM device
internally organized as 16Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAV25128 device. The device features
software and hardware write protection, including partial as well as
full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz SPI Compatible
• 2.5 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 64−byte Page Write Buffer
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• 8−Lead SOIC and TSSOP Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V_CC
SI
CS
WP
CAV25128
SO
HOLD
SCK
V_SS
Figure 1. Functional Symbol
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS
1
SO
WP
V_SS
V_CC
HOLD
SCK
SI
SOIC (V), TSSOP (Y)
Pin Name
CS
SO
WP
V_SS
SI
SCK
HOLD
V_CC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
October, 2012 − Rev. 0
Publication Order Number:
CAV25128/D