CAT1023LI-25-G Datasheet, PDF (1/21 Pages) ON Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer

CAT1021, CAT1022, CAT1023
Supervisory Circuits with I²C Serial 2k-bit CMOS
EEPROM, Manual Reset and Watchdog Timer
FEATURES
Precision Power Supply Voltage Monitor
— 5 V, 3.3 V and 3 V systems
— Five threshold voltage options
Watchdog Timer
Active High or Low Reset
— Valid reset guaranteed at V_CC = 1 V
400 kHz I²C Bus
2.7 V to 5.5 V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
— WP pin (CAT1021)
1,000,000 Program/Erase cycles
Manual Reset Input
100 year data retention
Industrial and extended temperature ranges
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8 mm
For Ordering Information details, see page 19.
DESCRIPTION
The CAT1021, CAT1022 and CAT1023 are complete
memory and supervisory solutions for microcontroller-
based systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection are
integrated together in low power CMOS technology.
Memory interface is via a 400 kHz I²C bus.
The CAT1021 and CAT1023 provide a precision V_CC
sense circuit and two open drain outputs: one (RESET)
drives high and the other (R¯¯E¯S¯E¯T¯) drives low whenever
V_CC falls below the reset threshold voltage. The
CAT1022 has only a R¯¯E¯S¯E¯T¯ output and does not have
a Write Protect input. The CAT1021 also has a Write
Protect input (WP). Write operations are disabled if WP
is connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit
that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. For the
CAT1021 and CAT1022, the watchdog timer monitors
the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5 V, 3.3 V and 3 V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply voltage
exceeds the reset threshold level. With both active high
and low reset signals, interface to microcontrollers and
other ICs is simple. In addition, the R¯¯E¯S¯E¯T¯ pin or a
separate input, ^{¯M¯R¯,} can be used as an input for push-
button manual reset capability.
The on-chip, 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a V_CC sense circuit that prevents writes to memory
whenever V_CC falls below the reset threshold or until V_CC
reaches the reset threshold during power up.
Available packages include an 8-pin DIP and surface
mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8mm maximum. TDFN footprint options are 3 x 3mm.
© 2009 SCILLC. All rights reserved.
1
Characteristics subject to change without notice
Doc. No. MD-3009 Rev. P